As is well known in the art, ferroelectric materials are materials that exhibit a spontaneous polarization in response to an applied electric field due to the atomic displacement of the body-centered atom in the perovskite (ABO3) structure. With these materials, a change in the direction of the electric field causes a change in the direction of the atomic displacement. Ferroelectric materials have two stable states, which makes these materials well-suited for use in memory applications. Furthermore, ferroelectric materials retain their polarization state after the applied electric field is removed. As such, ferroelectric materials may be used to fabricate non-volatile memory devices.
Ferroelectric memory devices may exhibit excellent endurance, high operation speeds (e.g., several tens of nano-seconds), low operation voltages (e.g., 5 Volts) and low standby currents (e.g., 1 mA). Based on these characteristics, ferroelectric memory devices are considered promising devices as the next-generation of semiconductor memory devices. However, the next-generation memory devices will need to be highly integrated devices. To provide such high integration, it may be necessary to secure reliable one-transistor/one-capacitor (1T/1C) cell structures, reduced size ferroelectric capacitors, multi-layer interconnection processes, hot temperature retention, read and write endurance equal to DRAM and SRAM memory devices and various other device characteristics.
Conventional dynamic random access memory devices do not include ferroelectric capacitors or other ferroelectric materials. As such, the methods used to fabricate ferroelectric memory devices may differ in various aspects from the methods that are used to fabricate conventional DRAM memory devices. By way of example, the polysilicon that is used in the fabrication of many conventional DRAM memory devices may react very actively with the ferroelectric material. As such, a noble metal, such as platinum (Pt), or a conductive oxide, such as ruthenium dioxide (IrO2), is often used to form the capacitor electrode in ferroelectric memory devices.
Like DRAM memory devices, ferroelectric memory devices may include a transistor and a ferroelectric capacitor that is electrically connected to the transistor. This connection may be established by a local interconnection that is formed of metal. An example of a method in which a local interconnection is used to electrically connect a transistor to a ferroelectric capacitor is disclosed in U.S. Pat. No. 5,119,154 entitled “FERROELECTRIC CAPACITOR AND METHOD FOR FORMING LOCAL INTERCONNECTION.”
Another method for establishing the interconnection between the transistor and the ferroelectric capacitor is to use a contact plug that is formed of a conductive material, such as polysilicon. An example of this method is disclosed in U.S. Pat. No. 5,854,104 entitled “PROCESS FOR FABRICATING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING A FERROELECTRIC CAPACITOR” that is assigned to Sharp Co. of Japan. This method may provide for higher integration of the ferroelectric memory cells.
In a ferroelectric memory device, it typically is desirable that the ferroelectric material have a crystalline structure, such as a perovskite structure, to provide the hysteresis characteristic in response to an applied external voltage. To achieve this crystalline structure, the ferroelectric material typically is thermally treated at a temperature of 550 degrees Centigrade or more after it is deposited. This thermal treatment may cause a thin insulating layer to form between the contact plug and the lower electrode, which may cause the contact resistance to increase. If a polysilicon contact plug is used, a silicon oxide layer may form between the contact plug and the lower electrode. To help avoid the formation of such a layer, an oxygen-diffusion barrier may be formed between the contact plug and the lower electrode of the ferroelectric capacitor.
FIGS. 1 and 2 are cross-sectional views of selected layers of a conventional ferroelectric memory device that schematically illustrate a method for fabricating a ferroelectric capacitor that has a conventional contact plug.
Referring to FIG. 1, a transistor (not shown) is formed on a semiconductor substrate (not shown) and then an interlayer insulating layer 11 is formed on the transistor and the semiconductor substrate. The interlayer insulting layer 11 is patterned to form an opening that exposes a drain region of the transistor in the semiconductor substrate. A conductive material such as, for example, polysilicon is deposited in the opening, thereby forming a contact plug 13. Next, a stacked capacitor structure 23 is formed on the interlayer insulating layer 11 and the contact plug 13. As shown in FIG. 1, the stacked capacitor structure may comprise an oxygen-diffusion barrier layer 15, a lower electrode layer 17, a ferroelectric layer 19 and an upper electrode 21 that are sequentially stacked on the interlayer insulating layer 11 and the contact plug 13.
As shown in FIG. 2, the stacked capacitor structure 23 is patterned to form a ferroelectric capacitor 25 that is electrically connected to the contact plug 13. However, etching damage 27 may occur in the ferroelectric layer 19 during the patterning processes. Specifically, as shown in FIG. 2, sidewalls of the ferroelectric layer 19 may be damaged during the etching of the lower electrode 17 and the oxygen-diffusion barrier layer 15 because the ferroelectric layer 19 is exposed during the etching of these layers. This etching damage 27 may cause degradation to the ferroelectric properties of the ferroelectric layer 19, thereby deteriorating the performance of the ferroelectric memory device. The impact of this etching damage 27 typically increases with an increasing degree of device integration. Moreover, the etching damage 27 to the ferroelectric layer 19 also tends to increase with increasing thickness of the oxygen-diffusion barrier layer 15. However, if the thickness of the oxygen-diffusion barrier layer 15 is reduced to minimize the etching damage 27, the oxygen-diffusion barrier layer 15 may not prevent oxidation of the contact plug 13 and, thus, the contact resistance may increase.